The present invention relates to a three-phase pulse-width modulated waveform generator, and in particular, it relates to a three-phase pulse width modulation generator used in pulse-width modulation (hereinafter, referred to as PWM) inverters that control alternating current motors and the like at variable speed.
A PWM inverter shown in FIG. 9 is generally used to control a three-phase motor. An alternating power source 301 is first converted to a desired DC voltage by an AC/DC converter circuit 302. Then the DC voltage is converted to three-phase AC voltage to be supplied to coils of motor 306 by switching six power transistors (represented by switches in FIG. 9) included in an upper arm 304 adjacent to a high-potential supply voltage and a lower arm 305 adjacent to a low-potential supply voltage. In FIG. 9, the upper arm 304 and the lower arm 305 construct a power module 303.
As shown in FIG. 10, a three-phase alternating voltage of U-phase, V-phase, and W-phase is reconstructed from a PWM voltage of U-phase, V-phase, and W-phase that is generated by modulating the pulse width of a triangular carrier signal. The six power transistors are driven by a U-phase PWM signal, a /U-phase PWM signal, a V-phase PWM signal, a /V-phase PWM signal, a W-phase PWM signal, and a /W-phase PWM signal outputted from a microcomputer-controlled three-phase pulse-width modulated waveform generator.
As shown in FIG. 11, the relationship between U and /U, V and /V, and W and /W needs to be complementary (when one is ON, the other is OFF). Specifically, the /U-phase PWM signal is the complementary signal of the U-phase PWM signal, the /V-phase PWM signal is the complementary signal of the V-phase PWM signal, and the /W-phase PWM signal is the complementary signal of the W-phase PWM signal. Two transistors that correspond to each other in the upper and lower arms are turned on and off complementarily for each of the U-phase, V-phase, and W-phase, thereby performing push-pull operation. The U-phase, V-phase, and W-phase needs to be displaced by an electrical angle of 120 degrees, as shown in FIG. 12.
When the upper arm 304 and the lower arm 305 formed by the six power transistors are turned on at the same time, short current or excessive current is caused to flow through both the upper and the lower arms 304 and 305. To prevent it, it is necessary to provide short-circuit prevention time, or dead time, for each of the U-phase, V-phase, and W-phase, between ON and OFF and between OFF and ON of the respective output waveforms of the U-phase PWM signal and the /U-phase PWM signal, the V-phase PWM signal and the /V-phase PWM signal, and the W-phase PWM signal and the /W-phase PWM signal. For example, Japanese Unexamined Patent Application Publication No. 10-112982 (FIG. 1) discloses a technique of generating a PWM waveform that has a dead time set in a delay circuit between ON and OFF and between OFF and ON of the upper arm and the lower arm.
Its structure is shown in FIG. 13. An up-down counter 401 is operated by a count clock 404. When the value of a rewritable comparing register 402 and the value of the up-down counter 401 are coincident with each other, a coincidence detection signal 408 is outputted from a comparator 403 into a delay circuit 405, and the delay circuit 405 starts the operation of counting the dead time for preventing a short circuit.
When a control signal 415 is outputted from an output-polarity control circuit 413 into the delay circuit 405 when the output polarity of the PWM signal is switched, then the delay circuit 405 starts to count the dead time. When the dead-time counting operation has been finished, a delay signal 410 is outputted from the delay circuit 405.
A waveform generation section 406 is supplied from the up-down counter 401 with a count direction signal 409 indicative of whether the counting direction is an up-count direction or a down-count one. In addition, the waveform generation section is also supplied with the coincidence detection signal 408, the delay signal 410, and a control signal 414 indicative of the output polarity of the PWM signal from the output-polarity control circuit 413. A U-phase PWM signal 411 and a /U-phase PWM signal 412 are outputted from the waveform generating section 406 via tristate buffers controlled by an output stop signal 407.
In positive polarity, the U-phase PWM signal 411 outputs logic level 1 according to the coincidence detection signal 408 during up-count and outputs logic level 0 according to the delay signal 410 by the coincidence detection signal 408 during down-count. In opposite polarity, the U-phase PWM signal 411 outputs logic level 0 according to the delay signal 410 by the coincidence detection signal 408 during up-count and outputs logic level 1 according to the coincidence detection signal 408 during down-count. It outputs logic level 1 according to the control signal 415 when the polarity is switched from the positive polarity to the opposite polarity and outputs logic level 0 according to the delay signal 410 by the control signal 415 when the polarity is switched from the opposite polarity to the positive polarity.
In positive polarity, the /U-phase PWM signal 412 outputs logic level 0 according to the delay signal 410 by the coincidence detection signal 408 during up-count and outputs logic level 1 according to the coincidence detection signal 408 during down-count. In opposite polarity, the /U-phase PWM signal 412 outputs logic level 1 according to the coincidence detection signal 408 during up-count and outputs logic level 0 according to the delay signal 410 by the coincidence detection signal 408 during down-count. It outputs logic level 0 according to the delay signal 410 by the control signal 415 when the polarity is switched from the positive polarity to the opposite polarity and outputs logic level 1 according to the control signal 415 when the polarity is switched from the opposite polarity to the positive polarity.
This structure ensures dead time for preventing a short circuit so that the power transistor in the upper arm and the power transistor in the lower arm are not turned on at the same time. As the same applies to the generation of the V-phase and /V-phase PWM signals and the W-phase and /W-phase PWM signals, a description thereof will be omitted here but the up-down counter 401 is shared among the three phases.
The power transistor in the upper arm and that in the lower arm are different from each other in drive ability, or switching time. Under the circumstances, in order to reduce the time that both of the power transistors in the upper arm and the lower arm are off and thereby to provide optimum complementary switching, it is necessary to individually set the dead time for the upper arm and the dead time for the lower arm.
The three-phase pulse-width modulated waveform generator of the related art, shown in FIG. 13, can select any dead time. However, the illustrated generator has only one delay circuit that determines the dead time and which is common to both the upper arm and the lower arm. In addition, the dead time can not be individually and controllably set at each of the upper and the lower arms. As a result, the dead time for the upper arm is identical with that for the lower arm.
Accordingly, a common dead time must be set for the upper arm and the lower arm in consideration of a longer switching time. This results in the problem of increasing the time that both of the power transistors of the upper arm and the lower arm are kept off and makes it difficult to achieve optimum complementary switching.
It has recently been required in controlling the inverter of an electric power steering system (EPS) and a hybrid electric vehicle (HEV) not only to allow the dead time for the upper and lower arms to be set individually but also to allow linear control of PWM duty (output width of PWM in one cycle of the carrier wave) from 0% to 100% output.
FIG. 14A shows a desired output signal. FIG. 14B shows an output that can be achieved by a related art. The /U-phase requires a PWM signal output shorter than the set dead time, or 0%, as shown as the area surrounded by the dotted line in FIG. 14A. However, in the related art, a PWM signal has a set dead-time width, as shown in FIG. 14(B) or is quickly changed to 100%.
As described above, the related art has not been allowed to provide output control within the range from a set dead-time width to 100%, or 0%. Accordingly, it cannot provide an ideal inverter control, shown in FIG. 15(A),due to generation of an uncontrollable range as in the inverter control of FIG. 15(B). This makes it difficult to linearly control the PWM duty from 0% output to 100% output.